1. Field of the Invention
The present invention relates to a data management device and a data management method for a large-block flash memory, which can improve inefficient data operation of the flash memory, which may be caused because a logical data operation unit is smaller than a physical data operation unit in a large-block flash memory.
2. Description of the Prior Art
In general, flash memories may be used as storage media for storing and processing data in embedded systems, such as electric home appliances, communication devices, set-top boxes, etc.
The flash memory is a nonvolatile storage device which data can be electrically erased from and rewritten into. As compared with storage media based on magnetic disk memories, the storage medium based on such a flash memory has an access time as fast as that of a hard disk while causing a smaller power consumption, and is suitable for portable devices owing to its small size.
In the flash memory, when new data are overwritten on pre-written data, a process of erasing the whole block, in which the pre-written data are stored, is required due to a hardware characteristic of the flash memory.
In order to prevent the performance deterioration of the flash memory, which may occur due to discordance between a data writing unit and a data erasure unit in the flash memory, concepts of a logical address and a physical address are introduced.
Herein, the logical address is an address used when a user requests a data operation, such as data reading, data writing, etc., in the flash memory through a predetermined user program, and the physical address is an address used when the flash memory actually performs the data operation, such as data reading, data writing, etc.
Flash memories are generally classified into small-block flash memories and large-block flash memories. The small-block flash memory has a characteristic that the size of an actually physical data operation unit is identical to that of a logical data operation unit, but the large-block flash memory has a characteristic that the size of an actually physical data operation unit is larger than that of a logical data operation unit.
As shown in FIG. 1, a general large-block flash memory includes a sector 11 which is a logical data operation unit, a page 12 which is a physical data operation unit, and a block 13 which is a data erasure unit.
One page in the large-block flash memory includes a plurality of sectors, while one page in the small-block flash memory includes only one sector.
As shown in FIG. 2, data management device of a large-block flash memory includes a user request section 21 for requesting a data operation of the flash memory using a predetermined logical address, a converting section 22 for converting the logical address, which is used when the data operation is requested, into a physical address by means of a mapping table, and an operating section 23 for performing a predetermined data operation in the flash memory through a device driver 24, which controls the operation of the flash memory according to the converted physical address.
In the following description, the operation of the data management device of the large-block flash memory having the above-mentioned construction will be explained with reference to FIG. 3. First, a user requests a data operation of the flash memory using a predetermined logical address (operation S1).
In this case, the user may request the data operation by means of a predetermined user program included in the user request section 21.
The logical address is converted into a physical address of the flash memory by a predetermined mapping table in the converting section 22 (operation S2).
The operating section 23 controls the device driver 24, which controls the operation of the flash memory, by the converted physical address, so that the data operation requested by the user is performed (operation S3).
Then, it is judged whether or not a data operation of all logical addresses used by the user has been completed (operation S4). As a result of the judgment, if the data operation of all logical addresses used by the user has not been completed, the next logical address is converted into a corresponding physical address (operation S5), operation S3 of performing the data operation is again performed with respect to the converted physical address.
That is, in the case of the large-block flash memory, when sectors, which are physical addresses corresponding to logical addresses used when the user requests a data operation, are included in different pages from each other, the operating section 23 accesses each page including each physical address according to the sequence of the physical addresses and performs the data operation.
Therefore, even when multiple physical addresses are included in the same page, if they are not sequential addresses, the operating section 23 repeatedly accesses the same page to perform a data operation.
In the following description, a data reading operation performed by the operating section 23 will be explained as an example of data operations.
First, if logical addresses used by the user are logical address ‘0’ to logical address ‘5’ and physical addresses corresponding to the logical addresses are positioned as shown in FIG. 4A, the operating section 23 performs the data operation first with respect to a physical address corresponding to logical address ‘0’, and then with respect to the respective physical addresses of logical address ‘1’, logical address ‘2’, logical address ‘3’, logical address ‘4’, and logical address ‘5’, in regular sequence.
That is, as shown in FIG. 4B, the operating section 23 accesses the respective pages including each physical address corresponding to each logical address in regular sequence, and performs the data operation with respect to the physical addresses corresponding to each logical address.
Here, even when multiple physical addresses exist in one page, if they are not sequential addresses, the operating section 23 performs the data operation with respect to only one physical address in a corresponding sequence.
Therefore, in order to perform data operation with respect to all of logical address ‘0’ to logical address ‘5’, it is necessary to perform page access six times in total.
That is, even when multiple physical addresses are included in the same page, if they are not sequential addresses, the data management device of the flash memory, as described above, repeatedly accesses the same page to perform the data operation of the respective physical addresses.
Therefore, the time required for a data operation increases due to repeated accesses to the same page, which deteriorates the performance of the flash memory.